Digital Design Engineer, RTL

This role involves working on both IP design and integration, including task planning, code and design reviews, and contributing to sub-system/chip-level integration. You'll collaborate closely with the architecture team to develop implementation strategies. Responsibilities include interacting with the subsystem team, planning SoC milestones, and implementing quality checks (IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). You'll work with cross-functional teams (verification, DFT, physical design, emulation, and software) to make design decisions and communicate project status. The position requires experience with multiple SoCs with silicon success and proficiency in ASIC design methodologies. The goal is to contribute to the innovation behind Google's products and shape the next generation of hardware.