SoC and IP Design Engineer
Job Summary
Job Description
Google Cloud seeks a SoC and IP Design Engineer to contribute to custom silicon solutions for direct-to-consumer products. Responsibilities include defining SoC/block level design documents, performing RTL development (Verilog/SystemVerilog), simulation and debug, participating in synthesis, timing/power closure, ASIC bring-up, and test plan/coverage analysis. Collaboration with multi-disciplinary teams is crucial. The role requires expertise in digital logic design, RTL design concepts, logic synthesis, and design verification. Preferred qualifications include experience with design sign-off tools, scripting languages (Python/Perl), and knowledge of interfaces like PCIe, UCIe, DDR, AXI, and ARM processors.
Must have:
- 3+ years experience in digital logic design
- RTL design in Verilog/SystemVerilog
- Logic synthesis and optimization
- Design verification and debug
- SoC/block level design documentation
Good to have:
- Experience with design sign-off tools
- Scripting languages (Python/Perl)
- Knowledge of PCIe, UCIe, DDR, AXI, ARM
- SoC architecture and formal verification
- High-performance/low-power design
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
- Experience in logic design and debug with Design Verification (DV).
Preferred qualifications:
- Experience with design sign off and quality tools (e.g., Lint, Cyber Defense Center (CDC), etc.).
- Experience with a scripting language like Python or Perl.
- Knowledge in one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
- Knowledge of SOC architecture and assertion-based formal verification.
- Knowledge of high performance and low power design techniques.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
- Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
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