Stage Ingénieur : Amélioration de la stratégie de vérification pour les interfaces de debug & NFC F/M

5 Months ago • All levels

Job Details

Contexte

Le département «Digital HW/SoC (System on Chip) » de l’unité de produit « Secure Connected Edge » basé à Caen recrute un stagiaire de fin d’étude sur une durée de 6 mois (commençant au premier trimestre 2025) afin d’améliorer la vérification des fonctionnalités de debug et de trace de nos composants NFC (Near Field Communication, communication en champ proche).

Ce stage se déroule au sein de l’équipe de conception et d’intégration numérique qui offre solutions et composants pour les marchés de la Téléphonie Mobile, du paiement sécurisé, de l’identification numérique, des objets connectés et des infrastructures NFC.

Cette équipe est en charge de délivrer des solutions qualifiées aux principaux acteurs de la Téléphonie et des Transactions Mobile. Le respect des livraison dans les temps établis et la qualité des blocs conçus sont la piliers de nos activités de conception. L’équipe de Conception est engagée dans toutes étapes Hardware (HW) du développement d’un composant : de ses étapes de spécifications aux étapes de mise en fonderie, validation, lancement de la production et support aux clients.


Nous recrutons un stagiaire de fin d’étude sur une durée de 6 mois afin d’amélioration de la couverture de test des fonctionnalités de debug et trace du CPU ARM Cortex M33 intégré.

Vos missions

Le(a) stagiaire prendra en charge/réalisera une ou plusieurs des missions suivantes :

  • Compréhension de l’architecture de debug et de trace utilisé pour le processeur CPU ARM Cortex M33 intégré
  • Compréhension de l’environnement de vérification existant et de l’infrastructure de test fourni par ARM
  • Proposition d’amélioration des méthodes de vérification des modules de trace et de debug
  • Amélioration de l’environnement de vérification et de la couverture fonctionnelle des fonctionnalités de debug et trace

Votre profil

  • Niveau d’études : Bac + 5, dernière année d’école d’ingénieur en spécialité Circuits Intégrés, Systèmes Electroniques Intégrés, Electronique, Micro-Electronique, Conception d’Objets Communicants, Systèmes embarqués, Systèmes Electroniques.
  • Connaissances requises en :
  • Connaissances en VHDL / Verilog, UVM, flot de conception numérique, FPGA et circuits imprimés, développement Objet (C++) et logiciel bas niveau (C, assembleur).
  • Un bon niveau d’anglais est exigé.

Context

The “Digital HW/SoC (System on Chip)” Design & Integration Team located in Caen within the Business Unit « Secure Connected Edge » is looking for an intern engineer for a 6-months period (starting first 2025 quarter) in order to improve verification of debug and trace functionalities of our NFC (Near Field Communication) components.

This internship is taking place within the Digital HW/SoC (System on Chip) Design & Integration Team for C&S Business Unit offering solutions for secure mobility and retail, secure payment and identity, IoT security, NFC infrastructure and Secure Embedded transactions. This Team is tasked with delivering High Quality solutions for Mobile Transactions to demanding Mobile customers. A commitment to one-time delivery and strong focus on design quality is the foundation of all we do. The Team is involved in all Hardware aspects of the design from Specifications to Tape-Out, validation, ramp to production and customer support.

Our chips embed an ARM Cortex M33 CPU and all the needed infrastructure for debug and trace functionalities.

We are looking for an intern for six months who will improve test coverage of debug and trace functionalities of the ARM Cortex M33 embedded into our Chips.

Your responsibilities

The trainee will be responsible for/perform one or more of the following tasks :

  • Understanding the debug and trace architecture used by the integrated ARM Cortex M33 CPU
  • Understanding the existing verification environment and the ARM verification infrastructure
  • Proposal of improvement of verification methods of debug and trace functionalities
  • Improvement of verification environment and functional coverage of trace and debug functionalities  

Your profile

  • Education level :  Master Degree / last year of engineering school in Integrated Circuits, Integrated Electronics Systems, Electronics, Micro-Electronics, IOT design, Embedded Systems, Electronics Systems.
  • Knowledge required in:
  • VHDL / Verilog, digital design flow, UVM, FPGA, C++, C
  • A good level of English is required, working in an international multi-site team.

More information about NXP in France...

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