Digital Design Engineer, RTL

2 Days ago • 3 Years + • Research & Development

Job Summary

Job Description

This role involves working on both IP design and integration, including task planning, code and design reviews, and contributing to sub-system/chip-level integration. You'll collaborate closely with the architecture team to develop implementation strategies. Responsibilities include interacting with the subsystem team, planning SoC milestones, and implementing quality checks (IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). You'll work with cross-functional teams (verification, DFT, physical design, emulation, and software) to make design decisions and communicate project status. The position requires experience with multiple SoCs with silicon success and proficiency in ASIC design methodologies. The goal is to contribute to the innovation behind Google's products and shape the next generation of hardware.
Must have:
  • Bachelor's degree in relevant field
  • 3+ years SoC experience with silicon success
  • Chip design flow experience
  • Verilog or SystemVerilog proficiency
  • ASIC design methodologies expertise
Good to have:
  • Micro-architecture experience
  • ARM based SoC knowledge
  • Debug (coresight) experience
  • Cross-domain understanding
  • Memory compression, interconnects, coherence, cache experience

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • 3 years of experience with multiple SoCs with Silicon success.
  • Experience with chip design flow.

Preferred qualifications:

  • Experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache.
  • Knowledge of ARM based SoC, Debug (coresight).
  • Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
  • Understanding of Verilog or System Verilog language.
  • Proficiency with ASIC design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

  • Work on both the IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration.
  • Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs.
  • Interact with the subsystem team and plan System-on-Chip (SoC) milestones, plan quality checks as part of SoC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
  • Work with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process.

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

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