Memory and I/O IP Design Engineer

Job Description

In Q4 2023, Intel®announced Altera® will be reported as a separate business unit beginning on January 1, 2024, with ongoing support from Intel®. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future. Altera®, an Intel® company, is hiring. Altera®'s IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Intel's FPGA devices. These solutions are provided as highly configurable intellectual property IP cores that are fully integrated with Altera®'s software CAD tool, Quartus Prime. The IP Cores we develop include Memory Interfaces (such as DDR5, LPDDR5, or HBM), custom chip-to-chip interfaces for high-speed ADC/DAC tiles (for radar processing), and leading-edge transceiver interfaces (to enable Ethernet, PCIe, and other protocols).

Altera®'s IP cores provide configurable access to the high-speed, high-bandwidth interfaces, leveraging dedicated and specialized silicon subsystems in the FPGA. The constantly rising speed and complexity of memory devices, chip-to-chip, and transceiver interfaces presents a challenging design problem that requires system level knowledge of silicon, software, IP, and customer applications. As an IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art memory interface, chip-to-chip, or transceiver-based IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for memory, chip-to-chip, or transceiver interfaces- RTL development- Device support and CAD tool integration- Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests).

• Hardware power-on and debug.

• New product release and rollout support.

• Customer technical support.

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork.

• Highly motivated to learn and adapt to fast-changing technologies and environments.

• Excellent problem-solving skills and attention to detail.

• Demonstrate fundamental values such as accountability, integrity, and a winning mindset.

• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations.

Qualifications

This is an entry level position and will be compensated accordingly. You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• BS degree or MS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or equivalent.

• 1 years of experience in Digital logic hardware (e.g. System Verilog, Verilog and/or VHDL) design or verification, and/or

• 1 years of experience in Software programming or scripting (e.g. C/C++ and/or Python).

Preferred Qualifications:

• 3+ year of experience with IP Integration, RTL Design, System Verilog, Verilog and/or VHDL.

• 3+ year of experience with software programming and/or scripting languages (e.g. C/C++ and/or Python).

• FPGA design experience.

• Experience with RTL simulation, timing closure, STA.

• Experience with Memory Interfaces, High-speed ADC/DAC, or Transceiver Protocols (e.g. Ethernet, PCIe).

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation Annual Salary Range for jobs which could be performed in Canada:CAD 77,610.00-116,390.00Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change...