Job Details:

Job Description: 

GPU and AI are emerging fields and are in high demand. A candidate will work on cutting edge technologies with highly talented and knowledgeable team. The person will get exposure to big ASIC designs and the challenges. Really exciting field for someone looking to make career in ASIC Design

This role involves developing logic design, register transfer level (RTL) coding, and simulation for graphics IPs, including graphics, compute, display, and media. You will be responsible for generating cell libraries, functional units, and the GPU IP block for integration into full chip designs.

You will participate in defining architecture and microarchitecture features of the block being designed, applying various strategies, tools, and methods to write RTL and optimize logic. The goal is to ensure the design meets power, performance, area, and timing objectives, as well as design integrity for physical implementation.

Additionally, you will review the verification plan and implementation to ensure design features are correctly verified across verification hierarchies. This includes driving unit-level verification and resolving failing RTL tests, implementing corrective measures to ensure feature correctness.

Finally, you will support SoC customers to ensure high-quality integration of the GPU block.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field with a minimum of 3 + years of industry experience, OR
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field with a minimum of 2 + years of industry experience.

Experience above must include: System Verilog and Experience in RTL logic design using System Verilog

Preferred Qualifications:

• C++, and familiarity with OVM or UVM methodologies, as well as Formal Verification techniques.
• Experience in design partitioning, microarchitecture trade-offs, and high-speed digital logic design with a focus on timing closure.
• Knowledge of 3D graphics, GPU’s.
• Competence in developing system simulation models and debugging RTL/tests in collaboration with cross-site teams.
• Proven experience working with validation engineers to develop functional validation and coverage test plans.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$121,050.00-$170,890.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.