Sr. FPGA Verification Engineer - Austin, TX

Trend Micro, a global cybersecurity leader, helps make the world safe for exchanging digital information. Fueled by decades of security expertise, world-leading global threat research and intelligence, and continuous innovation, our cybersecurity platform protects hundreds of thousands of organizations and millions of individuals across clouds, networks, devices, and endpoints

With 7,000 employees across 65 countries, and the world’s most advanced global threat research and intelligence, Trend Micro enables organizations to simplify and secure their connected world. TrendMicro.com

No sponsorship will be provided for work permit applications or renewals for this position now or in the future.

Position Summary:

Trend Micro is looking for a Sr. FPGA Verification Engineer to join our FPGA team in Austin, Texas. Trend Micro has been developing advanced multi-million gate FPGAs to accelerate network packet processing and security functions for over 20 years. The FPGA team develops leading-edge, high-performance implementations of encryption/decryption, pattern matching, and data extraction/analysis functions among others, as well as a number of system interfaces.

Responsibilities:

As the Sr. FPGA Verification Engineer, you will be responsible for the development of verification test bench, verification components, debugging failures and creating simulation cases at various levels that require the following skillsets, as well as leading/mentoring the small team of less senior Verification Engineers.

• UVM based testbench development for FPGA implementations

• Strong skills in debug, failure re-creation and root cause analysis

• Ownership of testbench development, including stimulus, driver, monitors, response checkers, assertions and coverage using system Verilog and advanced UVM methodology.

• Development of direct and constrained-random stimulus

• Understanding and analysis of RTL code, functional, assertion coverage results

• Efficient debugging and logic skills. Familiarity with major simulation and debug tool vendors is a plus.

• Improving and refining the verification process, methodology, and metrics

• Working with RTL engineers on defining and documenting Verification Requirements List

Qualifications:

• BS degree or higher in EE or CE

• 10+ years of design verification experience in either FPGAs or ASICs

• Excellent analytical, problem solving, communication, and leadership skills

• Ability to collaborate, communicate, and work in a team environment.

• Knowledge of simulation tools i.e. VCS, DVE.

• OOP, UVM and System Verilog experience.

• Verification flow enhancements using a scripting language such as Python.

• Experience integrating vendor provided VIPs in UVM testbench is a plus.

• Experience with AXI4 and AXI4-Stream is a plus.

• Experience with PCI-Express is a plus.

• Experience with Networking protocols i.e. Ethernet, IP, TCP/UDP is a plus

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