Lead a team of RTL engineers in designing complex machine learning compute IPs. This role requires understanding architecture specifications and collaborating with software and architecture engineers. Responsibilities include managing the design process from conception to production, ensuring functionality with verification and validation teams, providing input on synthesis and physical design, and guiding the team for optimal Power Performance Area (PPA). You'll work with SoC Design and cross-functional teams for successful IP implementation. The position involves leading the full development cycle of SoC subsystems (NPUs, GPUs, DSPs, or processors) and contributing to the innovation behind Google's products.