Senior Staff, DFT Architect - RAS (Reliability, Availability, Serviceability)

Please Note:

To provide the best candidate experience with our high application volumes, we limit applications to a total of 10 over 6 months. 

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What You’ll Do

Products & Solutions Planning (PSP) office is part of Samsung Semiconductor, Inc. (SSI), the industry's technology and volume leader in semiconductor products. PSP’s mission is to create product and technology plans to exceed customer and market expectations and to build and realize productization strategies to provide best-in-class silicon products and solutions to our customers.

We are looking for Senior DFT (Design-For-Testability) Architect to join our team in San Jose, CA. A successful candidate will be responsible for product yield and quality by defining DFT architecture for a product composed of logic and memory (DRAM). The candidate will also be responsible for telemetry architecture of the product.

Location: Hybrid, working onsite at our San Jose Headquarters 3-4 days per week with the flexibility to work remotely the remainder of your time with an average of 10-20% travel per month.

Reports to: Corporate VP, Product Planning

• Define the DFT architecture of a product composed of logic and memory (DRAM), ensuring alignment with business direction
• Define key performance indicator (KPI) target of the platform, such as yield, test coverage and test cost
• Define innovative DFT architecture for quick failure analysis
• Define architecture for silicon health monitoring and telemetry
• Lead technical discussion with customers
• Manage relationships with key stakeholders across various departments such as Engineering, Sales, Marketing
• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s Degree in Electrical or Computer Engineering or related Physical Science with 15+ years of experience or Masters in Electrical or Computer Engineering or related Physical Science with 13+ Years of Industry Experience or PhD  in Electrical or Computer Engineering or related Physical Science with 10+ years of Industry Experience Preferred.
• 15+ years of experience in DFT architecture and testing SoC/memory products
• Hands-on experience in failure analysis of memory products
• In-depth knowledge about 3D stacking and DFT solutions
• Good knowledge about silicon health monitoring and telemetry
• Strong analytical skills with experience in data analysis and interpretation
• RAS (Reliability, Availability, Serviceability) experience is a PLUS!
• Excellent communication and interpersonal skills
• Ability to work independently and as part of a team
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.
• Proficiency in Korean is a plus

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