RTL Design Engineer
Job Summary
Job Description
This RTL Design Engineer role at Google involves designing interconnect IP for Pixel System on a Chip (SoCs). Responsibilities include defining microarchitecture details (interface protocol, block diagram, data flow, pipelines), RTL development (SystemVerilog), debugging simulations, performing RTL quality checks (Lint, CDC, RDC, Synthesis, UPF), participating in synthesis and timing/power estimation, and collaborating with multi-disciplinary teams. The ideal candidate will have experience with Verilog/SystemVerilog, microarchitecture, and RTL quality check tool flows. The position focuses on delivering high-quality RTL for Google's next generation of hardware.
Must have:
- Bachelor's degree in related field
- 3+ years Hardware IP design (Verilog/SystemVerilog)
- 3+ years RTL quality check (Lint, CDC, RDC, Synthesis)
- Microarchitecture experience
- RTL development & debugging
Good to have:
- Master's/PhD in related field
- 7+ years RTL quality check experience
- 7+ years Hardware IP design experience
- ARM-based SoCs experience
- Perl/Python scripting
- Low power design experience
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with Hardware IP design using Verilog/System Verilog and microarchitecture.
- 3 years of experience with the Register-Transfer Level (RTL) quality check tool flows (e.g., Lint, CDC, RDC, Synthesis).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 7 years of experience with the Register-Transfer Level (RTL) quality check tool flows (e.g., Lint, CDC, RDC, Synthesis).
- 7 years of experience with Hardware IP design using Verilog/System Verilog and microarchitecture.
- Experience with ARM-based SoCs, ARM-protocols, interconnects and ASIC methodology.
- Experience with coding language like Perl or Python.
- Experience with low power designs.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, RTL, low power design methodology and evaluate design options with performance, power and area.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform Register-Transfer Level (RTL) development (e.g., SystemVerilog), debug functional/performance simulations.
- Perform RTL quality checks including Lint, CDC, RDC, Synthesis, UPF checks.
- Participate in synthesis, timing/power estimation.
- Communicate and work with multi-disciplined and multi-site teams.
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