This RTL Design Engineer role at Google involves designing interconnect IP for Pixel System on a Chip (SoCs). Responsibilities include defining microarchitecture details (interface protocol, block diagram, data flow, pipelines), RTL development (SystemVerilog), debugging simulations, performing RTL quality checks (Lint, CDC, RDC, Synthesis, UPF), participating in synthesis and timing/power estimation, and collaborating with multi-disciplinary teams. The ideal candidate will have experience with Verilog/SystemVerilog, microarchitecture, and RTL quality check tool flows. The position focuses on delivering high-quality RTL for Google's next generation of hardware.