Full Chip Physical Integration and CAD Engineer, Silicon

This role involves developing custom silicon solutions for Google's direct-to-consumer products. Responsibilities include developing all aspects of RTL2GDS for ASIC/Mixed signal chips, complete ownership of physical design integration and CAD flow for Mixed signal chip development, driving the closure of timing and power/Physical convergence of the design, contributing to physical design methodologies and automation scripts, and defining and implementing innovative schemes to improve Performance, Power, Area (PPA) and CAD methodology. The ideal candidate will have 10+ years of experience in ASIC physical design flows and methodologies in advanced process nodes, expertise in synthesis, Place and route (PnR), sign-off convergence, and physical verification. Experience with mixed-signal design is preferred.