ASIC DFT Engineer, Silicon

2 Weeks ago • 3 Years + • Research & Development

Job Summary

Job Description

As an ASIC DFT Engineer at Google, you will be part of a team developing custom silicon solutions for Google's direct-to-consumer products. You'll collaborate with RTL and Physical Designer Engineers, contributing to subsystem-level DFT scan and MBIST architecture across multiple voltage and power domains. Responsibilities include writing scripts to automate DFT flow, developing production-ready tests for the ATE flow, and working with DFT methodologies and tools like Tessent, ATPG, BIST, JTAG, and IJTAG. The role requires expertise in DFT methodologies and EDA tools, contributing to the innovation behind products used by millions worldwide. This position is based in Bengaluru, Karnataka, India.
Must have:
  • Bachelor's degree in Electrical/Electronics Engineering or equivalent
  • 3+ years DFT experience
  • Experience with Tessent and ATPG
  • Low Power designs, BIST, JTAG, IJTAG knowledge
  • Subsystem level DFT scan, MBIST architecture experience
Good to have:
  • DFT flow/methodology architecting/development
  • Collaboration with Design, PD, and STA teams
  • Python and TCL scripting skills

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience.
  • 3 years of experience in DFT methodologies.
  • Experience with DFT Electronic Design Automation (EDA) tools like Tessent.
  • Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.

Preferred qualifications:

  • Experience architecting/developing DFT flows and methodologies.
  • Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams.
  • Excellent scripting skills in languages like Python and TCL.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work with a team of Design for Testing (DFT) Engineers, working closely with Register-Transfer Level (RTL) and Physical Designer Engineers.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

  • Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains. 
  • Write basic scripts to automate the DFT flow.
  • Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow.

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