Senior ASIC Design Verification Engineer, TPU Compute
Job Summary
Job Description
- 7+ years ASIC verification experience
- SystemVerilog and UVM expertise
- Experience in digital logic verification at RTL
- Coverage closure and verification plan creation
- Master's or PhD in relevant field
- Memory subsystem verification experience
- Power aware verification and gate level simulations
- Post silicon bring-up experience
- ASIC standard interfaces and memory system architecture familiarity
- Bonus
- Equity
- Benefits
1 skill required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 7 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience in verifying digital logic at RTL using SystemVerilog for ASICs.
- Experience in memory subsystem design verification.
- Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and UVM.
- Identify and write different types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Execute the closure of coverage measures, identification of verification holes, and demonstration of progress towards tape-out.
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