PHY Design IP Integration Technologist

2 Days ago • Upto 1 Years • Research & Development • $132,000 PA - $189,000 PA

Job Summary

Job Description

This role involves contributing to the selection and procurement of PHY Design IPs, planning and roadmap definition, pre-silicon integration, and coordinating requirements with cross-functional teams. You'll also assist in post-silicon bring-up and validation. As part of the TPU interface design team, you will improve the performance and power of TPUs by driving the selection, integration, and execution of high-speed IO Design IPs. This highly cross-functional role requires specifying and meeting technical requirements and coordinating all aspects of IP integration across all phases of the silicon lifecycle. The work contributes to the innovation behind products used by millions worldwide.
Must have:
  • PhD in EE/CS or equivalent
  • Analog PHY design/integration experience (PCIe, UCIe, HBM)
  • Design integration flows and requirements experience
  • Contribute to PHY IP selection and procurement
  • Own PHY IP planning and roadmap
  • Drive pre-silicon integration of PHY IPs
Good to have:
  • Experience coordinating designs through the silicon lifecycle
  • Experience writing design specifications
  • Sourcing IPs from third-party vendors
  • Expertise in PCIe, UCIe, HBM, Ethernet

Job Details

Minimum qualifications:

  • PhD degree in Electrical Engineering, Computer Science, or equivalent practical experience
  • Academic, educational, internship or project experience designing or integrating analog PHY designs (e.g., PCIe, UCIe, or HBM PHYs)
  • Academic, educational, internship or project experience with design integration flows and requirements

Preferred qualifications:

  • Experience coordinating designs through the entire silicon product lifecycle
  • Experience writing design specifications
  • Experience sourcing IPs from third-party vendors
  • Expertise in one or more of the following standards: PCIe, UCIe, HBM, Ethernet

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the TPU interface design team, you will play a pivotal role in pushing the boundaries of technology to improve the performance and power of our TPUs. You will drive the selection, integration, and execution of our high speed IO Design IPs. In this highly cross-functional role, you will be tasked with specifying and meeting the technical requirements and coordinating all aspects of the IP integration across all phases of the silicon lifecycle.

The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

  • Contribute to PHY Design IP selection and procurement process.
  • Own PHY Design IP planning and roadmap definition.
  • Drive pre-silicon integration of PHY Design IPs.
  • Coordinate PHY Design IP requirements with cross-functional teams (e.g., Design, Verification, Physical Design, DFT, Post-Silicon).
  • Assist in post silicon bring-up and validation of PHY IP designs.

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About The Company

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

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