Senior Manager, ASIC Engineering - DFT

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We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

High performance computing, AI / ML have resulted in rapid transformation of semiconductor industry especially in datacenter, automotive , networking etc domains. This growth has been driving increasing needs for innovative and integrated ASIC services and solutions. Samsung Foundry is expanding ASIC Engineering to support this need in North America. 

This Senior Manager, Asic Engineering position will be responsible for overall chip design execution from spec to silicon, so the candidate should be familiar with Architecture / Micro Architecture / Synthesis, DFT, Design Verification, Physical Design, Timing Signoff etc and should be domain expert in one or more of the above domains, especially DFT, Test , ATPG , Binning, Yield, in system test, debug and diagnostic needs of the design with heavy customer Interactions

Location: Onsite at our San Jose headquarters 5 days a week 

Report to:  Senior Director - ASIC

Job #: 42022

• Solid experience in full chip DFT architecture / spec creation for monolithic / 2.5 D / 3D designs / product level testing
• Solid experience in DFT and Test insertion , especially big die implementation
• Solid experience in JTAG protocols, Scan, and BIST architectures like memory BIST, IO BIST, LBIST, Streaming Scan Network
• Solid knowledge of NOC ( Network on Chip from Netspeed / Arteris )
• Solid experience in post silicon validation , validating and debugging test vectors on ATE during silicon bringup.
• Solid experience in writing DFT timing constraints
• Solid experience of working closely with STA and PD engineers to close timing in test mode
• Solid experience in generating, verifying anf debugging test vectors
• Excellent communication skills
• Ability to work independently and mentor junior team members
• Complete other responsibilities as assigned.

What You Bring

• Bachelors in Electrical Engineering, Physics, or related Physical Science with 15+ years of experience or Masters in Electrical Engineering, Physics or related Physical Science with 13+ years of Industry Experience or PhD in Electrical Engineering, Physics, or related Physical Science with 10+ years of Industry Experience Preferred. Master’s in Business Discipline with Engineering Degree a plus.
• Experience in in DFT Insertion in ASIC or SoC Design, with hands on experience in large complex projects..
• Strong knowledge of DFT insertion, simulation in SoC / CPU / GPU Designs.
• Comfortable working with internal teams, external teams, and customers.
• Highly passionate and energetic.
• Excellent communication skills.
• Experience of having worked on monolithic / chiplet /2.5D / 3D designs with D2D and  HBM2/3 memory interfaces will be a plus
• Project management and deep technical customer interaction.
• Frequent customer and partner visits to include Domestic and International travel.
• Strong customer orientation, good communication and presentation skills.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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