About the job
As a Senior Test Engineer for CMOS Backplane, you will be responsible for the test development of the CMOS Backplane in the microLED-based display panel solutions. This role interfaces with the CMOS Backplane development and panel test teams to develop custom test solutions for our next-generation display panels. You will work closely with the display panel test development engineers and operations team to ensure optimal test time, capability, capacity, and cost for engineering and production test plans.
Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
The US base salary range for this full-time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .