Silicon Architecture/Design Engineer
Job Summary
Job Description
As a Silicon Architect/Design Engineer at Google, you'll contribute to the development of next-generation TPUs for AI/ML applications. Responsibilities include workload characterization, architecture specification, performance modeling, microarchitecture design, RTL design, power analysis, and collaboration with hardware/software teams. You'll also work on design verification, post-silicon testing, and debug strategies. The role requires expertise in accelerator architectures, data center workloads, programming languages (C++, Python, Verilog), and Synopsys/Cadence tools. Experience with performance modeling tools and knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies are preferred.
Must have:
- PhD in relevant engineering field
- Accelerator architecture & data center workload experience
- C++, Python, Verilog, Synopsys, Cadence proficiency
- Architectural modeling & RTL design
- Performance & power analysis
Good to have:
- 2+ years post-PhD experience
- Performance modeling tools experience
- Knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies
- High-performance & low-power design techniques
- AI techniques for Physical Design Convergence
1 skill required
Job Details
Minimum qualifications:
- PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience.
- Experience with accelerator architectures and data center workloads.
- Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.
Preferred qualifications:
- 2 years of experience post PhD.
- Experience with performance modeling tools.
- Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs.
- Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis.
- Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
- Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations.
- Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.
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