Staff Design Verification Engineer

4 Months ago • 2-5 Years • $113,300 PA - $167,610 PA

Job Summary

Job Description

Marvell seeks a Staff Design Verification Engineer to verify RTL designs. Must have experience with Verilog, SystemVerilog (UVM), and C programming. Familiarity with scripting languages and Linux is a plus.
Must have:
  • Verilog & SystemVerilog
  • UVM Experience
  • C Programming
  • Linux Familiarity
Good to have:
  • Scripting Languages
  • Python or Perl
  • Test Plan & Schedule
  • Review Committee
Perks:
  • Hybrid Work Model
  • Year-End Shutdown

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Compute, Custom, and Storage Business Unit provides custom solutions for high performance compute, server, network processing, and storage applications. CC&S products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.

What You Can Expect

In this role you’ll work day to day with RTL engineers to verify their design. You’ll run simulations using Synopsys VCS or a similar program, and then debug as needed until the design meets required specifications.

You’ll attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues. As you take responsibility for larger blocks, you may have to present to a review committee and explain your test plan and test schedule for those larger blocks.

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.

Basic Requirements

  • Experience with Verilog and SystemVerilog, preferably with UVM
  • Basic proficiency with the C programming language
  • Familiarity with scripting languages, e.g., Python or Perl
  • Basic knowledge of the Linux operating system

To be successful in this role you must be:

  • Diligent and detail oriented.
  • Self-motivated and able to handle assignments with limited supervision.
  • Willing to accept and work with differing opinions.
  • Able to learn on the fly and work in a fast-paced environment.

 

#LI-TM1

Expected Base Pay Range (USD)

113,300 - 167,610, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

#LI-TM1

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