Hardware Verification Engineer
Job Summary
Job Description
- 5+ years experience OR Bachelor's + 2 years OR Master's + 1 year
- 3+ years in test plan development, simulation, testing, and debugging
- Verilog/VHDL, C/C++, Python experience
- UVM/SystemVerilog experience
- Functional coverage development
- 8+ years experience OR Bachelor's + 5 years OR Master's + 3 years OR Doctorate
- Experience with formal verification tools (SVA)
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Networking opportunities
9 skills required
Job Details
Overview
Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. The Semi-custom and Central IP Silicon (SCIPS) team is seeking passionate, driven, and intellectually curious Hardware Verification Engineer who can work with cross-discipline teams to develop the environment and test cases to verify IP designs. The candidate should be passionate about developing systematic and efficient methods to detect hardware/software vulnerabilities.
Join our team and help create critical IPs for various Microsoft teams. You'll be developing custom silicon for a diverse array of systems, from cutting-edge consumer products like Xbox to Azure cloud servers, clients, and IoT SOCs
Microsoft’s mission is to empower every person and every organization on the planet
to achieve more. As employees we come together with a growth mindset, innovate
to empower others and collaborate to realize our shared goals. Each day we build on
our values of respect, integrity, and accountability to create a culture of inclusion
where everyone can thrive at work and beyond.
Qualifications
Required Qualifications:
- 5+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience or internship experience.
- 3+ years of experience in developing test plans, creating simulation environments, developing tests, and debugging for multiple IPs, SoCs or systems.
- Technical experience in coding languages including, but not limited, to in Verilog or VHDL, C/C++, Python, Ruby or Perl.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- 8+ years technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $98,300 - $193,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $127,200 - $208,800 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft will accept applications for the role until February 10, 2025.
#CSCPJOBS
Responsibilities
- Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers to deliver functionally correct design.
- Identify and write functional coverage for stimulus and corner cases.
- Close coverage to plug verification holes and meet tape out requirements.
- Other
- Embody our and .
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