Design Verification Engineer, ASIC

This Design Verification Engineer role at Google involves planning and executing verification of next-generation configurable Infrastructure Intellectual Property (IPs), interconnects, and memory subsystems. Responsibilities include creating and enhancing constrained-random verification environments using SystemVerilog and UVM, developing cross-language tools and verification methodologies, identifying and writing coverage measures, and debugging tests with design engineers. The ideal candidate will have a Bachelor's degree in Electrical Engineering or Computer Science (Master's preferred) and 5+ years of experience in coding, test methodologies, test plans, test cases, and debugging, with experience verifying digital logic at the RTL level using SystemVerilog, C, or C++. The role contributes to the development of custom silicon solutions for Google's direct-to-consumer products.