Hardware Engineer 2

Do you want to be at the forefront of innovating the latest hardware designs to propel Microsoft’s cloud growth? Are you seeking a unique career opportunity that combines both technical capabilities, cross team collaboration, with business insight and strategy?

Join our Strategic Planning and Architecture (SPARC) team within Microsoft’s Azure Hardware Systems & Infrastructure (AHSI) organization and be a part of the organization behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.  

Microsoft delivers more than 200 online services to more than one billion individuals worldwide and AHSI is the team behind our expanding cloud infrastructure. We deliver the core infrastructure and foundational technologies for Microsoft's cloud businesses including Microsoft Azure, Bing, MSN, Office 365, OneDrive, Skype, Teams and Xbox Live. 

The SPARC organization manages Azure’s hardware roadmap from architecture concept through

production for all of Microsoft’s current and future on-line services. 

We are looking for a Hardware Engineer II to join the System Architecture team focusing on power and performance aspects of Microsoft’s Azure hardware systems deployed in various data centres across the globe

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Required/minimum qualifications

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field AND 2+ years technical engineering experience

  • OR Master’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field

  • OR equivalent experience

•  2+ years of experience in SOC power architectural trade-off analysis or design

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

• Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Additional or preferred qualifications

• 4+ years related technical engineering experience
• OR Master's Degree in Electrical Engineering, Computer Engineering AND 2+ years technical engineering experience
• OR Bachelor's Degree in Electrical Engineering, Computer Engineering, AND  4+ years technical engineering experience
• Deep understanding of computer architecture, SOC and system-SW architectures, and their power/performance tradeoffs.
• Experience developing SOC power and performance modeling techniques and benchmarks from conception to microarchitecture specification to post-silicon validation.
• Understanding of memory and interconnect sub-systems.
• Experience in development of analysis tools written in C++ and Python.
• Knowledge of performance monitors and post-silicon SOC power and performance tuning.
• Familiarity with ASIC power analysis, low power design and power optimization.
• Experience with cloud platforms such as Azure
• Proficiency in scripting languages such as Python, Bash, or PowerShell.
• Excellent problem-solving skills and attention to detail.
• Proficient communication and collaboration skills.
• Working knowledge of prevailing LLM models and frameworks like Tensorflow, Pytorch is a plus
• Familiarity with visualization and reporting tools like PowerBI is a plus

Hardware Engineering IC3 - The typical base pay range for this role across the U.S. is USD $98,300 - $193,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $127,200 - $208,800 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 23, 2025

#SPARC

• Work with business, architecture, and design teams to understand power and performance requirements and collaborate across functional teams to meet these needs in technology development planning and path finding.
• Work with platform, firmware, and software teams across Microsoft to identify opportunities to improve system power and performance management with a goal of improved power efficiency across the stack.
• Develop in-house power and performance modelling methodology and tools for Machine Learning systems.
• Project and report power constrained SOC performance results to senior management.
• Maintain the power modeling infrastructure, used for power constrained performance projections.
• Work with IP Micro-architects and RTL team to incorporate low power design methodologies and power saving techniques. Identify IP/SOC power saving opportunities and drive definition of power saving uArch features.
• Understand product SOC power and performance interactions with power delivery and thermal solutions at the system level.
• Use case profiling, cloud computing workload analysis and PnP modeling, and correlation to post-silicon.
• Apply your growth mindset to learn and adapt in a complex and dynamic environment.
• Identify performance bottlenecks, optimize resource utilization, and implement improvements to enhance performance.
• Come up with dashboards to maintain Power-Performance visualization and build infrastructure for improving the analysis framework
• Guide teams in designing, building, testing, and deploying changes to existing software.
• Identify manual processes that can be automated.
• Consider the organization’s entire infrastructure when making changes and improvements.
• Collaborate with team members to define product requirements and implementation.
• Embody our and