Package Design Engineer - Power Integrity Lead

As a Power Integrity leader in the Advanced Packaging design team, you will be responsible for the following: 

• Power Delivery Network (PDN) design and optimization within 2D/2.5D/3D packages 

• Power Integrity Analysis and simulation of package designs and advanced studies 

• Providing thought leadership on advanced packaging techniques and advancing Marvell's capabilities and understanding of industry trends 

• Interfacing with product design teams for optimized floor-planning, package related design oversight and power delivery network design 

• Design flow optimization and development for cycle-time reduction and quality assurance 

This job requires working a hybrid schedule, on-site for a minimum of two (2) days per week with one of Marvell's packaging design teams in either Santa Clara, CA, Westlake Village, CA, Boise, ID, Ottawa, Ontario or Burlington, VT. 

The ideal candidate will have expert level knowledge as a Power Integrity engineer as well as in-depth knowledge of Signal Integrity concepts and design strategies.  

In addition, the candidate will possess a bachelor’s degree in Electrical Engineering or related fields and 15+ years of related professional experience or master’s degree and/or PhD in Electrical Engineering or related fields with 12+ years of experience. 

Marvell is looking for an individual contributor with demonstrated success in the following areas:  

• Evaluating designs for challenging electrical requirements 

• Close interaction with packaging layout engineers and IP teams to optimize electrical performance 

• Simulation tasks, as well as new EDA tool evaluations, design flow development and scripting for efficiency and automation. 

Skills needed to be successful in this role:  

• Advanced knowledge of signal integrity and power integrity 

• Experience with power plane design, modeling and analysis using tools like PowerSI, SIwave 

• Expertise in system-level power integrity modeling, extractions, and circuit simulations 

• Experience with at least one of the following programming languages: TCL, Java, Python, Perl, Skill, C++ 

• Ability to work with engineers in multiple locations and geographies 

• Strong communication, presentation and documentation skills 

The ideal candidate would have: 

• Experience with 2.5D/3D package development, including interposer design 

• Experience in power integrity methodology and workflow development for cross-functional teams  

• Experience with VNA and TDR measurements for packages and PCBs characterization 

• Experience with ADS and HSPICE circuit simulation 

• Familiarity with packaging technologies, materials, package substrate design rules and assembly rules 

• Understanding, debugging and simulations of EMI/EMC problems 

• Working knowledge of Voltus die model generation