Physical Design Timing Engineer

Job Description:

Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs. Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

Qualifications:

Minimum Qualifications:

B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience.

Preferred Qualifications:

At least 8+ years of experience in physical design/SOC level/SS Top level using industry EDA tools.

Experience in Python/Perl/TCL programming languages.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.