Senior Silicon Design Engineer

1 Hour ago • 7-11 Years • Research & Development

About the job

Job Description

Microsoft's Silicon team seeks a Senior Silicon Design Engineer to lead microarchitecture and RTL implementation of custom IP blocks. Responsibilities include defining microarchitecture specifications, developing RTL, and running static checks, synthesis, and timing analysis. Collaboration with design verification engineers and architects is crucial. The ideal candidate possesses extensive experience in digital logic design using Verilog/SystemVerilog and familiarity with synthesis/static check tools. This role involves working on leading-edge custom IP development within the Semi-Custom and Central IP Silicon (SCIPS) team.
Must have:
  • 7+ years experience in relevant engineering
  • 3+ years in digital logic design (SystemVerilog/Verilog/VHDL)
  • 3+ years running synthesis/static check tools (RTL synthesis, lint, CDC, RDC, LEC)
  • Lead microarchitecture and RTL implementation of custom IP blocks
Good to have:
  • 11+ years technical engineering experience
  • Experience with various synthesis and static check tools
Perks:
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Networking opportunities

Overview

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.  
 
We are looking for a Senior Silicon Design Engineer to work on leading edge custom IP development as part of the Semi-Custom and Central IP Silicon (SCIPS) team. The candidate should excel at collaborating with other engineers to solve complex technical challenges. 
 
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.  

 

Qualifications

Required Qualifications:

7+ years of related technical engineering experience

o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

  • 3+ years experience in digital logic design in SystemVerilog/Verilog/VHDL 
  • 3+ years experience running synthesis/static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC.

 

Other Requirements:

 

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:

 

Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 

 

Preferred Qualifications:

 

11+ years technical engineering experience

o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

 

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 15, 2025.

 

#ahsi #SHPE24MSFT #SCHIE

Responsibilities

You will be responsible for leading the microarchitecture and Register Transfer Level (RTL) implementation of custom IP blocks, working with a group of other design team members, design verification engineers, and architects.  Individuals will be working on defining microarchitecture specifications, developing RTL, and running static checks, synthesis, and timing analysis.  Experience with Verilog/System Verilog required. 

Embody our and 

 

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
Industry leading healthcare
Educational resources
Discounts on products and services
Savings and investments
Maternity and paternity leave
Generous time away
Giving programs
Opportunities to network and connect
View Full Job Description
$117.2K - $250.2K/yr (Outscal est.)
$183.7K/yr avg.
Mountain View, California, United States

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About The Company

Microsoft is a tech giant that develops, licenses, and supports a range of software products, services, and devices.

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