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Silicon Design Verification Engineer, TPU, Google Cloud

Karnataka, India (On-site)

Silicon Design Verification Engineer, TPU, Google Cloud

2 Months ago • 4-6 Years • Research & Development • Undisclosed

About the job

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Job Description

As a Silicon Design Verification Engineer, you will play a pivotal role in shaping the future of AI/ML hardware acceleration. You'll be responsible for verifying complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems. Your contributions will directly impact the reliability and performance of Google's TPU hardware, which powers some of the most demanding AI/ML applications. You'll own the full verification life cycle, including planning, test execution, coverage closure, and ensuring adherence to stringent AI/ML performance and accuracy targets. You'll also collaborate closely with design and verification engineers on active projects. This role involves building robust, constrained-random verification environments using SystemVerilog and UVM to identify and expose corner-case bugs.

Must have:

Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as Universal verification methodology (UVM).
2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
Experience with SystemVerilog, SVA, and functional coverage.

Good to have:

Master's degree in Electrical Engineering or a related field.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with the full verification life cycle.
Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
Excellent problem solving and communication skills.

Minimum qualifications:

Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as Universal verification methodology (UVM).
2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
Experience with SystemVerilog, SVA, and functional coverage.

Preferred qualifications:

Master's degree in Electrical Engineering or a related field.
Experience with industry-standard simulators, revision control systems, and regression systems.
Experience with the full verification life cycle.
Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
Excellent problem solving and communication skills.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will own the full verification life cycle, from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy targets. Build robust, constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Measure to identify verification holes and to show progress towards tape-out.
Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM).

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