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Package Design Engineer - Power Integrity Lead

Marvell

Vermont, United States (On-site)

Package Design Engineer - Power Integrity Lead

6581 Years ago • 15 Years +

About the job

Summary_{By Outscal}

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Marvell Advanced Packaging team is responsible for supporting customers with package designs that meet challenging electrical requirements. High speed signaling and challenging power delivery networks require complex and custom solutions to meet constantly advancing application needs. Many of the new designs require multi-chip and multiple component configurations with high-speed IP requirements. In addition, our team is advancing Marvell's expertise in 3D packaging, Co-packaged optics and cutting-edge substrate materials. We work with the world's leading manufacturers to solve our client's most challenging designs and integrations with industry-leading packaging techniques.

What You Can Expect

As a Power Integrity leader in the Advanced Packaging design team, you will be responsible for the following:

Power Delivery Network (PDN) design and optimization within 2D/2.5D/3D packages

Power Integrity Analysis and simulation of package designs and advanced studies

Providing thought leadership on advanced packaging techniques and advancing Marvell's capabilities and understanding of industry trends

Interfacing with product design teams for optimized floor-planning, package related design oversight and power delivery network design

Design flow optimization and development for cycle-time reduction and quality assurance

This job requires working a hybrid schedule, on-site for a minimum of two (2) days per week with one of Marvell's packaging design teams in either Santa Clara, CA, Westlake Village, CA, Boise, ID, Ottawa, Ontario or Burlington, VT.

What We're Looking For

The ideal candidate will have expert level knowledge as a Power Integrity engineer as well as in-depth knowledge of Signal Integrity concepts and design strategies.

In addition, the candidate will possess a bachelor’s degree in Electrical Engineering or related fields and 15+ years of related professional experience or master’s degree and/or PhD in Electrical Engineering or related fields with 12+ years of experience.

Marvell is looking for an individual contributor with demonstrated success in the following areas:

Evaluating designs for challenging electrical requirements

Close interaction with packaging layout engineers and IP teams to optimize electrical performance

Simulation tasks, as well as new EDA tool evaluations, design flow development and scripting for efficiency and automation.

Skills needed to be successful in this role:

Advanced knowledge of signal integrity and power integrity

Experience with power plane design, modeling and analysis using tools like PowerSI, SIwave

Expertise in system-level power integrity modeling, extractions, and circuit simulations

Experience with at least one of the following programming languages: TCL, Java, Python, Perl, Skill, C++

Ability to work with engineers in multiple locations and geographies

Strong communication, presentation and documentation skills

The ideal candidate would have:

Experience with 2.5D/3D package development, including interposer design

Experience in power integrity methodology and workflow development for cross-functional teams

Experience with VNA and TDR measurements for packages and PCBs characterization

Experience with ADS and HSPICE circuit simulation

Familiarity with packaging technologies, materials, package substrate design rules and assembly rules

Understanding, debugging and simulations of EMI/EMC problems

Working knowledge of Voltus die model generation

Expected Base Pay Range (USD)

182,300 - 269,730, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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