STA/Timing Methodology Engineer

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Overview:

Experienced STA/Timing Engineer with 3-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes.

Job Description:

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.

• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

• Evaluate multiple timing methodologies/tools on different designs and technology nodes.

• Work on automation scripts within STA/PD tools for methodology development.

• Good Technical writing and Communication skills. Willing to work in cross-collaborative environment.

• Experience in design automation using TCL/Perl/Python.

• Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

• Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

Preferred Qualification/Skills

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.

• Hands-on experience with STA tools - Prime-time, Tempus

• Have experience working on timing convergence at Chip-level and Hard-Macro level.

• In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

• Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus)

• Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.

• Proficient is scripting languages – TCL, Perl, Python

• Basic knowledge of device physics

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