Timing Engineer, Senior Staff

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

• As ASIC Timing Engineer you will be responsible for post RTL design flow.
• You will be responsible for block and /or chip level synthesis, timing closure, DFT generation and ECOs.
• Improve the design methodology and flow.
• Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Collaborate with Analog / Digital design teams to deliver competitive SerDes IP solutions across all product lines.
• Provide support to product teams, both pre-silicon and post-silicon.

What We're Looking For

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related fields with 6+ years of relevant experience, or a Master’s/PhD with 3+ years of experience.
• Solid post-RTL experience, including synthesis, timing analysis, and physical design.
• Ability to perform custom placement and routing for mixed-signal designs.
• Flexibility to work across all post-RTL design activities as needed.
• Good understanding of block and top-level physical timing closure.
• Proficient in logic or physical synthesis using Synopsys or Cadence tools.
• Skilled in static timing analysis with Primetime.
• Experienced in physical design for 28nm technology and beyond.
• Knowledgeable in Design-for-Test (DFT) generation and verification.
• Strong Perl and Tcl scripting skills.
• Experience in low-power design techniques.
• Familiarity with IR drop analysis.
• Background in circuit-level or custom design.
• Knowledge of floorplanning, clock-tree synthesis, and power planning/analysis.
• Understanding of signal integrity and physical verification.
• Experience developing Place and Route (PnR) flows.
• Strong communication skills and effective team collaboration abilities.
• Motivated to be part of a highly skilled design team.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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