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ASIC Engineer, Design Verification

ASIC Engineer, Design Verification

1 Month ago • 5-5 Years • Research & Development

About the job

10 skills required for this role

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shell

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networking

cross-functional

Job Description

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. You will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. Responsibilities include: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Must have:

Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
Track record of 'first-pass success' in ASIC development cycles
5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Good to have:

Experience in development of UVM based verification environments from scratch
Experience verifying GPU/CPU designs
Experience with micro-architectural performance verification
Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
Experience with verification of ARM/RISC-V based sub-systems or SoCs
Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet
Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
Experience working across and building relationships with cross-functional design, model and emulation teams
Experience with revision control systems like Mercurial(Hg), Git or SVN

Perks:

Bonus
Equity
Benefits

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Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.

Develop functional tests based on verification test plan.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.

Track record of 'first-pass success' in ASIC development cycles.

5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications

Experience in development of UVM based verification environments from scratch.

Experience verifying GPU/CPU designs.

Experience with micro-architectural performance verification.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with verification of ARM/RISC-V based sub-systems or SoCs.

Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.

Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Experience with revision control systems like Mercurial(Hg), Git or SVN.

For those who live in or expect to work from California if hired for this position, please click for additional information.

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Locations

Data Center

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

$142,000/year to $203,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about at Meta.

Equal Employment Opportunity and Affirmative Action

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice .

Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to .

View Full Job Description

$142.0K - $203.0K/yr (Outscal est.)

$172.5K/yr avg.

Sunnyvale, California, United States

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