Senior Engineer High-Speed I/O Analog-Mixed Circuit

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What You’ll Do

DRAM Design Lab(which includes Memory I/O Development) is part of Samsung’s Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory I/O Development’s vision is to provide a next generation memory interface technology solution which can be adopted in DDR, LPDDR, GDDR, and HBM products. We are an integral part of Samsung’s paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps.

Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing

Location: Hybrid with at least 4 days in office in San Jose, CA office location remainder of time to work remotely.

Job ID: 42474

•  Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but   are not limited to the following: high-speed data converters, PLL, and SERDES.
  • Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary.
  • Ownership of circuit and system specifications.
  • Simulate designs with state-of-the-art CAD tools.
  • Document designs and simulation results.

What You Bring

• MS  3+years of experience or PhD in Electrical Engineering, Computer Science preferred.
  • 3+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
  • Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, HBM I/O interface.
  • Needs to be an expert in providing and understanding layout requirements of high speed circuits.
  • Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed          power design and low power design.
  • Experience working closely with device/process team to define transistor specs
  • The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment.
  • Ability to troubleshoot and analyze complex problems.
  • Excellent communication (written and verbal) and interpersonal skills
  • Experience in high frequency clock distribution design, implementation, and analysis.
  • Deep understanding of PPA (performance, power, and area) trade-offs.
  • Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools
  • Experience on silicon bring-up and automatic measurement using script
  • Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus.
  • Self-motivated problem-solver with an ability to work well in a team.
  • You’re inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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