NVIDIA seeks a Senior STA Engineer to own full-chip STA, analyze timing results, generate timing constraints for complex interfaces, and resolve timing/congestion problems in high-speed communication devices.  Responsibilities include SDC generation and review, STA tool usage, guiding chip closure, and participating in flow development and new technology implementation.  The ideal candidate possesses 5+ years of experience in RTL2GDS flows and methodologies, with expertise in STA, physical design, and EDA tools (Synopsys, Cadence).  The role involves collaboration with front-end, DFT, and back-end teams to shape the SoC clock tree and contribute to groundbreaking chip designs.

Explore gaming industy jobs in one of the leading Game Studios.

NVIDIA

System Software Engineer - Android Platform Security

System Software Engineering Manager

Senior Silicon Solution Engineer - Hardware

Senior System Validation Engineer

Senior System Performance and Power Engineer

Circuit Design Engineer

Senior System Integration Engineer

Senior System Software Engineer - AI Performance and Efficiency Tools

Staff Systems Software Engineer - Server

M&A and Integration Lead

<div data-automation-id="jobPostingDescription" class="css-4r17ng">NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.What you'll be doing:<ul><li>Own the full chip STA, analyze the timing results, verify correctness and provide budget for the different partitions.</li><li>Generate the timing constraints of complex interfaces for the STA and the P&amp;R flow.</li><li>Be exposed and work on a variety of exciting designs (including high cell count and high frequency), resolving complex timing and congestion problems.</li><li>Help to shape the SoC clock tree, and effect the work of the different teams (Front end, DFT &amp; BE).</li><li>Daily work involves all aspect of STA &amp; chip design: take part in SDC generation &amp; review, actively running &amp; analyzing STA tools, guiding the group during chip closure process, etc'.</li><li>Taking part inflows development.</li><li>Take part in ramping up new breaking technologies.</li></ul>What we need to see:<ul><li>B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.</li><li>5+ years proven experience in RTL2GDS flows and methodologies.</li><li>Knowledge in physical design flows and methodologies with emphasis on STA (PNR, STA, physical verification).</li><li>Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).</li><li>Excellent teammate.</li></ul>NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.</div>

Senior STA Engineer