The Senior Staff Engineer will be responsible for delivering standards-compliant IP blocks for CXL/PCIE in FPGAs or ASICs, leading ASIC or FPGA projects, and streamlining the ASIC development process. The role involves designing, developing, and documenting the design using Verilog and the verification environment using System Verilog and UVM, developing test cases, and managing bug reports. The engineer will also be involved in staffing, employee development, and fostering teamwork. This position reports to the Director of the Design Team.