Sr Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview:

As an integral member of the Formal Verification Application Engineering team, you will work with industry leading semiconductor and system companies to deploy Cadence’s market leading Jasper Formal Verification products. You will work with the EMEA based AE and sales teams to provide technical support in the Pre and Post-Sales process.

In this pivotal role you will be a front-line contact with Cadence customer’s engineers and CAD teams and will the following responsibilities:

Job Responsibilities:

• Providing technical support for the deployment of Cadence’s market leading Jasper Formal Verification products.
• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support.
• Working with the various Cadence sales teams and product developers to develop innovative solutions to address customer’s challenging problems.
• Providing proactive support and problem consultation to make our product users successful.
• Collaborating with R&D to introduce new formal flows and Apps to customers.
• Championing customer needs and helping R&D to develop competitive and creative technical solution.
• Applying formal property checking tools to diverse functional verification problems.
• Fostering a collaborative, team-oriented, work environment.

Job Qualifications:

• BEng in Electronic / Micro-Electronic Engineering or Computer Science – or equivalent.
• Experience of Hardware Design and Verification languages including PSL, SVA, Verilog, VHDL, System Verilog, System-C, TLM.
• Experience of the IP/ Soc verification process.
• Experience with Unix / Linux environment including scripting languages.
• Good Communication skills.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

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