ASIC RTL Design Engineer

2 Hours ago • 10-12 Years • $141,300 PA - $226,000 PA

Job Summary

Job Description

The ASIC RTL Design Engineer will be responsible for the design and development of digital circuits, including defining the architecture. This role requires experience in micro-architecture, RTL development, and knowledge of architecture definitions related to clocks, resets, and interconnects. The engineer should have worked on ARM-based SoC and possess knowledge of Lint, CDC, SDC, and verification strategies at the SoC level. Strong interpersonal skills and teamwork are also essential.
Must have:
  • Bachelor's or Master's degree in relevant field.
  • Experience in SOC architecture and design.
  • Experience with micro-architecture and RTL development.
  • Knowledge of clocks, resets, and interconnects.
  • Experience with ARM-based SoC.
  • Knowledge of Lint, CDC, SDC, and verification strategies.
  • Strong experience with Verilog and System Verilog.
  • Experience in Tcl, Perl, and Python scripting.
  • Understanding of ASIC design flow.
Good to have:
  • Verification experience is a plus.
  • Experience in chip-to-chip communication protocols is a plus.
Perks:
  • Medical, dental, and vision plans.
  • 401(K) participation with company matching.
  • Employee Stock Purchase Program (ESPP).
  • Employee Assistance Program (EAP).
  • Paid holidays.
  • Paid sick leave and vacation time.
  • Paid Family Leave.

Job Details

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Job Description:

We are seeking for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining the architecture.

Requirements:

  • Bechelor's Degree in Electrical Engineering, Computer Engineering or Computer Science and 12+ years of meaningful experience in SOC architecture and design experience or Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science and 10+ years of meaningful experience in SOC architecture and design experience.

  • Verification experience is a plus.

  • Experience in micro-architecture and RTL development.

  • Worked on architecture definitions on clocks, resets, interconnects, IO interfaces.

  • Worked on ARM based SoC

  • Should have knowledge on Lint, CDC, SDC, Verification strategy at SoC level.

  • Experience in chip-to-chip communication protocols in MCM case is a huge plus

  • Comfortable in solving the architecture problems from micro-architecture to system level.

  • Strong experience with Verilog, System Verilog

  • Strong experience in Tcl, Perl, Python scripting

  • Good understanding of ASIC design flow

  • Strong interpersonal skills and an excellent team player

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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About The Company

A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.

 

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