Senior Member of Technical Staff

Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work closely with architects, micro-architects to develop a test plan to be executed for verifying the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments and building test benches in UVM, SV and C. Responsible for developing tests - both directed and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the verification environment. Develop UVM/SV/C based checks for functional correctness, including transaction order, transaction payload construction and transaction responses. Run regressions, debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the fixes in a timely manner. Generate coverage for the design, analyze and close any gaps. Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely with Firmware and Software teams to test the firmware images/ software to be run with PCIe design. Support all verification activities and the SoC through successful tape out. Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the team on PCIe verification activities.