CPU Debug and Power Management Verification Engineer

Apple

| Beaverton, Oregon, United States (On Site) | Full Time | 5 months ago

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Job Summary

The CPU Debug and Power Management Verification Engineer will be responsible for verifying the auxiliary features of a high-performance ARM-based CPU. This includes Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers. The role involves working across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug. The engineer will collaborate with architecture and RTL designers, develop and execute test plans, write and debug tests, build verification infrastructure, analyze functional coverage, and identify design issues. They will also support SoC-level debug and work with silicon bring-up teams.

Must Have

Verify functionality correctness of CPU Power Management and debug logic.
Develop and execute test plans and schedules.
Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages.
Build and maintain verification infrastructure, including checkers and monitors.
Analyze functional coverage to ensure test plan completeness.

Job Description

We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers—spanning both ARM-standard capabilities and Apple-specific innovations. • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs. • Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic • Develop and execute test plans and schedules • Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments • Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors. • Analyze functional coverage to ensure test plan completeness • Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes • Support SoC-level debug for clock and power integration issues • Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.