Signal Integrity Engineer/Layout, Senior Staff

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Central Engineering - AMS Signal Integrity Signal Integrity Team is responsible for establishing and maintaining interconnect Signal Integrity (SI) and Power Integrity (PI) design rules for Marvell COMPHY, D2D, DDR and other analog misc. IP. This includes overseeing floorplan, Redistribution Layer (RDL) design, bump pattern, package routing, and PCB layout to ensure optimal system performance.

What You Can Expect

• Collaborating with cross-functional teams: Work closely with circuit design, applications engineering, packaging technology, and board design teams to define and implement system interconnects that meet both internal specifications and customer requirements.
• Conducting simulations and analysis: Perform SI/PI simulations and analysis to predict and mitigate potential issues in the design phase.
• Developing SI/PI design rules: Create and maintain design rules for floorplan, RDL, bump patterns, package, and PCB layouts to ensure signal and power integrity across the system.
• SI/PI model release: Release Die models including IBIS-AMI, power current profiles and on-die decoupling caps to internal BU and external customer.
• Providing technical support: Offer technical support and guidance to other teams and customers regarding SI/PI issues and best practices.

What We're Looking For

• Bachelor’s degree in electrical engineering and 8+ years of related professional experience or Master’s degree/PhD in electrical engineering with 5+ years of experience.
• Must have good knowledge about interposer/package/PCB design rules, routing feasibility and SI consideration. Experiences in die-to-die interposer, package and PCB high density trial routing study by using Cadence tool such as APD or PCB editor are required. EM modeling skills is preferred.
• IO circuits (board, chip and transistor level), high speed digital design, PCB layout, Package and interposer technology.
• Experience in interfaces such as DDR, Nand, PCIe/Ethernet or other high-speed parallel/serial bus is a plus
• Always do the right thing and represent Marvell with ethics and integrity.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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