Sr. Memory Layout Design Engineer

2 Months ago • 6-10 Years • Software Development & Engineering

Job Summary

Job Description

The Sr. Memory Layout Design Engineer is responsible for high-quality layout design and verification of memory circuits. This involves understanding and applying layout guidelines, process rules, and other technical requirements. The engineer will be responsible for schedule time-line & layout floor-planning, completing quality layout and verification within planned schedule. They will also need to quickly learn new methodologies, communicate effectively within the library team, and may lead or train junior engineers. The role requires expertise in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and ElectroMigration in CMOS processes. The ideal candidate will have experience with Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools, along with experience in Floor-planning, hierarchy layout and chip integration. The candidate should have good leadership quality on project management.
Must have:
  • Strong layout knowledge with 6-10 years of experience
  • Bachelor's degree
  • Experience with Cadence layout and schematic capture
  • Proficiency in CALIBRE & Hercules verification tools
  • Experience in digital (standard cell, memory, I/O) layout
  • Strong experience in memory layout design and physical verifications
  • Experience in Cadence Layout tools VIRTUOSO and CALIBRE verification tools
  • Good experience in Floor-planning, hierarchy layout and chip integration
Good to have:
  • Experience in analog layout
  • Knowledge of Script Programming and SKILL Programming
  • Experience in the memory compiler

Job Details

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Job Description:

Requirements:

  • Strong layout knowledge with a minimum of 6 to 10 years of experience
  • Applicants must hold a Bachelor's degree
  • Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
  • Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc
  • Experienced in digital (standard cell, memory, I/O) layout
  • Experienced in analog layout is also a plus

Job Description:

  • Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
  • Schedule time-line & layout floor-planning
  • Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
  • Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

  • Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process.
  • Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
  • Good experience in Floor-planning, hierarchy layout and chip integration.
  • Knowledge of Script Programming and SKILL Programming would be a plus.
  • Able  to lead  or train a team of junior engineers
  • Good knowledge on memory layout topology.
  • Experience in the memory compiler will be a plus.
  • Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
  • Self-reliant, with ability to work independently as well as a team.
  • Good leadership quality on project management.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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