GPU Functional Verification Senior Engineer
Job Summary
Job Description
- Develop deep understanding of GPU pipeline
- Develop UVM based System Verilog TB
- Strong communication skills
- Ability to learn and deliver
- Minimum 3 years verification experience
- Knowledge of GPU pipeline design
- Proficiency with formal tools
- Working knowledge of property based FV
4 skills required
Job Details
In the role of GPU Functional Verification Engineer, your project responsibilities will include the following,
- Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces
- Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices
- Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality
- Collaborate with worldwide architecture, design, and systems teams to achieve all project goals
Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver
Experience
- Minimum 3 years of Design verification experience
- Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above
Education Requirements
- BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities
Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR.
The pre-Si verification team in Bangalore is currently heavily involved in the following
- UVM/SV based constrained random test bench for functional verification
- Subsystem level TB for complete GPU workload analysis and compliance
- Emulation platforms to analyze performance and pipeline bottlenecks
- Formal tools – both for reduced time to bug & property based FV sign-off
- Power Aware & Gate level simulations to deliver a high-quality GPU implementation
- Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug
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