Physical Design Engineer, Senior

18 Hours ago • 2-3 Years

Job Summary

Job Description

As a Physical Design Engineer, Senior at Qualcomm, you will be responsible for the PNR implementation including floor planning, placement, CTS, and post-route on the latest nodes. You will need to demonstrate knowledge of signoff processes, including STA, power analysis, FV, low power verification, and PV. This role involves collaborating with cross-functional teams, optimizing designs, and ensuring product quality and performance. The candidate should have good hands-on experience on Floorplanning, PNR and STA flows, good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc, good understanding on signoff domains and good knowledge on Unix/Linux.

Must have:

Floorplanning, PNR and STA flows experience
Placement/Clock Tree Synthesis (CTS) knowledge
Signoff domain knowledge (STA, Power Analysis)
Unix/Linux - Perl/TCL fundamentals/scripting

5 skills required

5 skills required for this role

Add these skills to join the top 1% applicants for this job

unix

perl

linux

fpga

cross-functional

Job Details

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Minimum Qualifications:

Good hands-on experience on Floorplanning, PNR and STA flows

Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc

Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc

Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting

Principal Duties and responsibilities:

Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.

Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)

Quick learner with good analytical and problem solving skills

Qualifications:

• 3+ years Hardware Engineering experience or related work experience.

• 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

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