CPU Physical Design Engineer

3 Days ago • All levels

Job Summary

Job Description

As a CPU Physical Design Engineer at Qualcomm, you will collaborate with the microarchitecture and RTL design team to implement designs. The responsibilities include understanding specifications, performing feasibility studies, synthesizing Verilog RTL, performing synthesis, place & route, and optimizing designs. Additionally, you'll validate designs for functionality and electrical robustness. This role requires working with industry-standard tools and optimizing designs to meet timing, power, and area goals. Knowledge of CPU microarchitecture, high-performance, and low-power implementation methods is preferred.

Must have:

Knowledge of CPU microarchitecture.
Experience in deep submicron process technology nodes.
Knowledge of library cells and optimizations.
Understanding of tools for synthesis, place & route and tapeout flows.
Experience with synthesis, place and route and signoff timing/power analysis.

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cross-functional

Job Details

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.

As a CPU Physical Design Engineer, you will work with microarchitecture and RTL design team to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.

Roles and Responsibilities

Work with CPU microarchitecture team to understand specifications and design trade offs in pipeline and structure sizing.
Perform feasibilities to validate implementability, area, timing and power.
Synthesize the Verilog RTL into gate level designs and perform optimizations.
Perform SynthPlace & Route on the designs using industry standard tools and deliver GDS.
Optimize the design at various stages from RTL to GDS to meet timing, power and area goals.
Validate the designs for functional and electrical robustness.

Preferred qualifications

Knowledge of CPU microarchitecture.
Experience in deep submicron process technology nodes is strongly preferred.
Knowledge of library cells and optimizations.
Solid understanding industry standard tools for synthesis, place & route and tapeout flows.
Experience with Synthesis, place and route and signoff timing/power analysis.
Knowledge of high performance and low power implementation methods
Knowledge of CPU microarchitecture, logic design and circuits

Physical Requirements

Frequently transports between offices, buildings, and campuses up to ½ mile.
Frequently transports and installs equipment up to 5 lbs.
Performs required tasks at various heights (e.g., standing or sitting).
Monitors and utilizes computers and test equipment for more than 6 hours a day.
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.