Senior Principal Digital IC Design Engineer

1 Month ago • 8-15 Years • Software Development & Engineering • $168,920 PA - $253,000 PA

Job Summary

Job Description

Marvell's semiconductor solutions are essential for data infrastructure. As a Senior Principal Digital IC Design Engineer, you will design hardware for data centers and AI SOCs. Responsibilities include shaping micro-architecture, writing specifications, RTL coding, collaborating with verification teams, aiding physical design, and supporting post-silicon bring-up. The role involves working with multiple design centers and the software team. This role requires experience in various aspects of chip development and strong collaboration skills.
Must have:
  • Fluent in System Verilog RTL coding techniques.
  • Familiar with modern SoC architectures and interface technologies.
  • Experience in micro-architecture of complex custom/ASIC products.
  • RTL design experience, synthesis, and functional verification.
Good to have:
  • Experience in implementation/timing closure for high speed design.
  • Hands-on experience for all aspects of chip-development process.
  • Experience in designing high speed embedded processor SOC products.
  • Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell.
Perks:
  • Flexible time off
  • 401k
  • Year-end shutdown
  • Floating holidays
  • Paid time off to volunteer

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Our design team works on state-of-the-art datacenter and AI SOCs. As a member of the R&D team, you will design world-class hardware for the industry's largest customers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

In this role, you will:

  • Shape the micro-architecture of the chip 

  • Write specifications and define micro-architecture of the design 

  • Implement designs using low-power RTL coding techniques 

  • Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug

  • Work with the physical design team in aiding the implementation of the functional blocks

  • Interact with the project manager to scope and assign tasks

  • Work with multiple design centers and design groups to shape future methodology

  • Support the post silicon team to bring up silicon in the lab

  • Work with the software team to ensure product meets customer use cases

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Or Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. Or PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

To be successful in this role you will need to be:

  • Fluent in System Verilog RTL coding techniques.

  • Familiar with modern SoC architectures and various interface technologies such as AXI, HBM, Ethernet, PCIe, D2D.

  • Experience in micro-architecture of complex custom/ASIC products focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general purpose microprocessors. 

  • RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.

  • Experience in implementation/timing closure for high speed design.

  • Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a plus.

  • Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.

  • Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

#LI-TM1

Expected Base Pay Range (USD)

168,920 - 253,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

#LI-TT1

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About The Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

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