SOC Clock Implementation Engineer
Job Summary
Job Description
Join a well-funded hardware startup as an SOC Clock Implementation Engineer. The company aims to revolutionize silicon and create Risc-V based SOC computing platforms. This role involves defining clock methodology, influencing clock architecture, planning and implementing clocking solutions, developing simulation models, and performing physical implementation for the SOC. You will also develop and maintain the clock tree synthesis flow, analyze clock tree quality, and conduct clock verification. Collaboration with RTL, Integration, Block level, LEC, STA, Power, EMIR, and LV teams is essential. The company offers a creative and flexible work environment.
Must have:
- 5-7 years of experience in clock methodology development for high-performance SoCs in advanced process nodes.
- Experience with clock architecture planning and clock tree synthesis flow.
- Experience with custom clocking solutions, quality metrics, and clock verification.
- Experience with synthesis, place & route, STA, and Spice.
- Strong knowledge of CMOS circuits and low-power design.
- Working knowledge of EM, IR, and top-level integration.
- Working knowledge of Verilog/SystemVerilog.
- Strong scripting skills (TCL/Python).
- Excellent problem-solving, communication, and organizational skills.
- Ability to work cross-functionally and meet aggressive schedules.
1 skill required
Job Details
Join a cutting-edge and well-funded hardware startup as an SOC Clock Implementation Engineer. Our mission is to reimagine silicon and create Risc-V based SOC computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
Responsibility
- Define clock methodology to influence early clock arch changes, plan and implement clocking solutions, develop simulation models, and physical implementation for the SOC.
- Develop and maintain clock tree synthesis flow for block consumption.
- Analyze clock tree quality and clock verification.
- Engage with RTL, Integration, Block level, LEC, STA, Power, EMIR and LV teams.
Requirements
- 5-7 years of experience with clock methodology development for high performance SoCs in advanced process nodes (7/5/3nm).
- Experience with clock arch planning, clock tree synthesis flow, implementing custom clocking solutions, quality metrics and clock verification.
- Experience with synthesis, place & route, STA and Spice.
- Strong knowledge of CMOS circuit, low power design.
- Working knowledge of EM, IR, Top-level integration.
- Working knowledge with verilog/system verilog.
- Strong scripting skills preferably in TCL/Python.
- Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
- Self starter and highly motivated
- Ability to work cross-functionally with various teams and be productive under aggressive schedules
Education and Experience
- BS with 7 years / MS with 5 years of experience
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