Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Meet the team:
The Baseband Modem Design group, in HYD, is primarily responsible for designing and developing cutting-edge WIFI modem solutions which are integrated into low-power/line-powered SoCs used in Wireless-IOT products. The group is responsible for the RTL implementation of the new WIFI standards required in the IOT space market. The team actively collaborates with signal processing experts in defining the algorithms and implementing them. The team also verifies core modem functionality and works with extended Verification team to verify all the System level usecases involving the baseband modem. It also handles the pre-Si and post-Si validation.
Responsibilities:
Develop complex communications or signal processing blocks for wireless-IOT products. Understanding of OFDM/signal processing is strongly desired
Collaborate with System Engineers to drive the definition of wireless blocks to meet product requirements. Proficiency in Matlab/C is strongly preferred
Micro-architecture and RTL design of modules using Verilog/System Verilog HDL coding, adhering to quality standards.
Prepare and hold Architecture, Design, and Verification reviews with technical staff throughout project lifecycle
Pre-silicon verification utilizing a combination of block/chip-level test benches.
Validation/bring-up of designs on silicon, providing support to cross-functional teams
Apply Low-power digital circuit design concepts
Skills required:
Demonstrated ability to work with Systems team to micro-architect and design complex digital subsystems
Understand Matlab algorithm implementation and translate to effective RTL micro-architectures
Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production
Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers (like vc, Questasim), and power analysis tools
Experience with logic synthesis, timing constraints and timing closure
Experience in working with backend team to optimize design for power performance and area
Experience with scripting and automation. Knowledge of Python, Perl, and Tcl
Experience with revision control and configuration management systems (such as Perforce, Git, Methodics)
Excellent written and verbal communications skills
Demonstrated ability to generate high output in a self-driven manner
Experience Level:
4-6 years in Industry
Education Requirements:
Master’s /Bachelors degree in Communications/Electronics Engineering
Benefits & Perks :
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
Equity Rewards (RSUs)
Employee Stock Purchase Plan (ESPP)
Insurance plans with Outpatient cover
National Pension Scheme (NPS)
Flexible work policy
Childcare support
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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.
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