Memory Layout Design Engineer

1 Hour ago • 3-4 Years

Job Summary

Job Description

The Memory Layout Design Engineer will be responsible for understanding and applying layout guidelines, new process rules, and technical requirements for quality layout. This includes schedule time-line and layout floor-planning, and completing quality layout and verification within the planned schedule. The engineer must also be able to get up to speed quickly with new methodologies and communicate well with others. Strong experience in memory layout design and physical verifications is required. The candidate should also possess good experience in floor-planning, hierarchy layout and chip integration and the ability to lead or train a team of junior engineers. Self-reliance and good leadership qualities are also necessary.
Must have:
  • Strong layout knowledge with 3-4 years of experience
  • Bachelor's degree is required.
  • Skills include Cadence layout, schematic capture, CALIBRE & Hercules verification tools.
  • Strong layout knowledge in submicron processes (16nm, 7nm, 5nm, 3nm, etc.)
  • Experienced in digital layout (standard cell, memory, I/O).
  • Strong experience in memory layout design and physical verifications (LVS, DRC, ERC, etc.).
  • Experienced in Cadence Layout tools VIRTUOSO and CALIBRE verification tools.
  • Good experience in Floor-planning, hierarchy layout and chip integration.
Good to have:
  • Experienced in analog layout is a plus.
  • Knowledge of Script Programming and SKILL Programming is a plus.
  • Knowledge on memory layout topology is a plus.
  • Experience in the memory compiler is a plus.
  • Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.

Job Details

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Job Description:

Requirements:

  • Strong layout knowledge with a minimum of 3 to 4 years of experience

  • Applicants must hold a Bachelor's degree

  • Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.

  • Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc

  • Experienced in digital (standard cell, memory, I/O) layout

  • Experienced in analog layout is also a plus

Job Description:

  • Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout

  • Schedule time-line & layout floor-planning

  • Complete quality layout and verification within planned schedule (without supervision for experienced engineer)

  • Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

  • Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, ElectroMigration in CMOS process.

  • Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.

  • Good experience in Floor-planning, hierarchy layout and chip integration.

  • Knowledge of Script Programming and SKILL Programming would be a plus.

  • Able  to lead  or train a team of junior engineers

  • Good knowledge on memory layout topology.

  • Experience in the memory compiler will be a plus.

  • Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.

  • Self-reliant, with ability to work independently as well as a team.

  • Good leadership quality on project management.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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About The Company

A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.

 

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