Staff Engineer - IP Design

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Alphawave Semi is expanding its team in PCIe IP design and development! We are looking for talented RTL Design Engineers to contribute to enhance and develop our IP. This is an incredible opportunity to be part of the PCIe and CXL development cycle, from specification to design.

As an RTL Design Engineer, you will work in IP design and integration. You will be responsible for microarchitecture, RTL coding, create microarchitecture documents, Lint and Synthesis cycle and Timing closure. You will work with verification team on achieving test plan, the code & functional coverage.

What You'll Do

• Deliver standards-compliant PCIe IP block.
• Will work on Micro-architect and document the design.
• Develop RTL design using Verilog and/or System Verilog.
• Work closely with the verification team in reviewing test suite/plans.
• Issue and track bug reports from launch to closure.
• Will refine IP development process with advancing tools/scripting.
• Work with our external customers or internal engineers to deliver designs for use.
• Collaborate with the team.
• You will be reporting to Principal Engineer of the Design team.

What You'll Need

• B.E/M.Tech with 8+ years of experience in IP, ASIC or FPGA development.
• Knowledge and experience in any serial protocols and AMBA (AHB, AXI and CXS) protocol.
• Experience working on PCIe/CXL protocol is advantageous.
• Solid experience with Verilog, and System Verilog.
• Experience with FPGA development cycle is desirable.
• Experience with Lint, CDC, Synthesis, Timing closure, FPGA validation, Power analysis and LEC tools.
• Experience in ASIC tape-outs is a plus.
• Good experience with debugging tools and solid debugging skills.
• Experience with Unix/Linux Shell scripting and/or Perl, TCL, Python and C/C++ programming.
• Strong communication skills.

"We have a flexible work environment to support and help employees thrive in personal and professional capacities"

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Competitive Compensation Package
• Restricted Stock Units (RSUs)
• Provisions to pursue advanced education from Premium Institute, eLearning content providers
• Medical Insurance and a cohort of Wellness Benefits
• Educational Assistance
• Advance Loan Assistance
• Office lunch & Snacks Facility