Senior Mixed Signal Design Engineer

6 Months ago • 5 Years + • Software Development & Engineering

Job Summary

Job Description

NVIDIA seeks a Senior Mixed Signal Design Engineer to contribute to the design and implementation of high-speed interface circuits, including transceivers and PLLs. Responsibilities involve mixed-signal circuit design, simulation, verification, and leading mask designers. The role requires hands-on lab experience with silicon validation, debugging, and characterization. Collaboration with multi-functional teams and taking designs through implementation and productization are crucial. A strong understanding of CMOS processes and related circuit design issues is essential.
Must have:
  • 5+ years CMOS analog/mixed-signal design experience
  • Cadence custom design tools proficiency
  • Data Converters, Tx, Rx, CDR, PLL design experience
  • Silicon bring-up and debugging expertise
  • Leadership and mentorship skills
Good to have:
  • System-level timing, signal, and power integrity knowledge
  • Verilog, Matlab, Nanotime experience

Job Details

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. Make the choice to join us today.

We are now looking for a Senior Mixed Signal Design Engineer. As a member of our Mixed Signal team, you are responsible for architecture definition and design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on experience in the lab with silicon validation, debugging, characterization and bring up is desired.

What you’ll be doing:

  • You will be part of the design and implementation of high speed interface circuits

  • Have the chance to create projects including high speed transceivers and high frequency PLLs

  • Become involved in the design, simulation, and verification of mixed-signal circuits

  • Lead mask designers, provide mentorship for floorplan and layout design

  • Provide support to the lab characterization of silicon, and pursue the challenges of circuit design in deep submicron CMOS

  • You will take designs through implementation and productizing; Collaborate with multi-functional teams

What we need to see:

  • BS or MS in Electrical Engineering (or equivalent experience), PhD preferred.

  • 5+ years of design experience in CMOS analog / mixed-signal circuit

  • Working knowledge of Cadence custom design tools, circuit simulator, timing analysis tool

  • Someone who's an exceptional teammate with good interpersonal skills. Validated experience in leading and mentoring designers

  • Your extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high speed IO interfaces. In-depth understanding of deep submicron CMOS process and related circuit design issues

  • Proven experience in silicon bring-up, debugging and use of lab instrumentation is required. Knowledge in system level timing budget, signal integrity, and power integrity is a plus

  • Experience in Verilog, Matlab, Nanotime is helpful

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.

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About The Company

Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.

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