CPU Physical Design-Timing Engineer

1 Month ago • 6-8 Years • Software Development & Engineering

Job Summary

Job Description

As a CPU Physical Design-Timing Engineer, you will be part of the P-Core design team, driving Intel's latest CPUs. Your responsibilities include timing analysis and convergence for complex partitions, ensuring timing execution for over 5GHz frequency and low-power designs, and collaborating with other teams. You will be responsible for Static Timing Analysis and handle high-speed designs, while ensuring Timing signoff flows using tools like Synopsys/Cadence. Also, you must handle new feature feasibility studies. This role is for an on-site presence.
Must have:
  • Master’s degree in Electrical/Electronics Engineering with at least 6 years of experience.
  • Experience in Static Timing Analysis is preferred.
  • Experience in handle complex core design, high-speed designs
  • Timing signoff flows/tools experience both/either Synopsys/Cadence tools
  • Very good knowledge on Timing tools, flows and methodology
  • Ability to handle new feature feasibility studies
  • Strong verbal and written communication skills
Good to have:
  • SD flow knowledge would be a plus
  • Familiarity with Verilog/VHDL
  • Tcl, Perl, Python scripting

Job Details

Job Details:

Job Description: 

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions.

Your responsibilities will include but not limited to:

1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs.

2. Deep understanding of Static timing analysis concepts

3. Timing Convergence across all HVM targets

4. Closely work with SD, Integration and Floor plan teams

Qualifications:

Qualifications

Qualifications

·       You must possess a master’s degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor’s degree with at least 8 years of experience.

·       Technical Expertise in Static Timing Analysis is preferred.

Preferred additional skills

·       Experience of handle complex core design, high-speed designs

·       Timing signoff flows/tools experience both/either Synopsys/Cadence tools

·       Very good knowledge on Timing tools, flows and methodology

·       Ability to handle new feature feasibility studies

·       SD flow knowledge would be plus

·       Familiarity with Verilog/VHDL

·       Tcl, Perl, Python scripting

·       Strong verbal and written communication skills

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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