Physical Design Engineer, Staff

2 Days ago • 3-5 Years

Job Summary

Job Description

As a Physical Design Engineer, you will be responsible for hands-on PD execution at the block/SoC level, focusing on improvements in Performance, Power, and Area (PPA). You will also be involved in rolling out robust methodologies, identifying areas for flow improvement, and providing support to the physical design team. This includes tool support, issue debugging, and developing productivity enhancement routines. The role also requires an understanding of advanced technology PNR and STA concepts, collaborating with EDA vendors, and a strong programming experience. The job involves working with Innovus/fc/icc2 tools and demands team collaboration and excellent communication skills.

Must have:

Hands-on PD execution at block/SoC level.
Strong understanding of PD Flow Methodology.
Proficiency in Python/Tcl/C++.
Experience with Innovus/fc/icc2 tools.
Knowledge of Encounter/Innovus or FC tool.

Good to have:

Basic understanding of Timing/Formal verification/Physical verification/extraction.
Ability to ramp-up in new areas
Excellent communication skills.

6 skills required

6 skills required for this role

Add these skills to join the top 1% applicants for this job

python

fpga

communication

team-player

cross-functional

problem-solving

Job Details

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

* Hands on PD execution at block/SoC level along with PPA improvements

* Strong understanding of the technology and PD Flow Methodology enablement.

* Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies.

(area/power/performance/convergence), develop plans and deploy/support them

* Provide tool support and issue debugging services to physical design team engineers across various sites

* Develop and maintain 3rd party tool integration and productivity enhancement routines

* Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions.

Skill Set

* Strong programming experience & Proficiency in Python/Tcl/C++

* Understand physical design flows using Innovus/fc/icc2 tools

* Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory

* Basic understanding of Timing/Formal verification/Physical verification/extraction are desired

* Ability to ramp-up in new areas, be a good team player and excellent communication skills desired

Experience

3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required

Niche Skills

Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

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