Silicon Validation Engineer

The Silicon Validation Engineer will lead efforts to bring up, validate, and characterize high-speed SerDes blocks. They will need hands-on experience with various high-speed SerDes architectures, including NRZ and PAM, as well as associated protocols. The role requires in-depth knowledge of crucial SerDes blocks such as CTLE, DFE, FFE, CDR, and PLLs, and their characterization and debugging processes. Proficiency in using test and measurement equipment like high-speed oscilloscopes and BERTs is essential, along with understanding SerDes adaptation techniques and analyzing SerDes signal integrity. The engineer will also be involved with high-speed protocols such as USB, PCIe, and DP. Strong debugging and problem-solving skills with data investigation and mining expertise are needed, as is the development of robust test methodologies to evaluate performance and calculate high-speed serial interfaces (SerDes) operating margins across PVT variations. They will also be supporting ATE and Product Engineering.

Must Have

• Experience with high-speed SerDes architectures (NRZ and PAM).
• Knowledge of SerDes blocks (CTLE, DFE, FFE, CDR, PLLs).
• Proficiency in using test and measurement equipment.
• Understanding of SerDes adaptation techniques and signal integrity.
• Experience with high-speed protocols (USB, PCIe, DP).